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產業動態 Key Enabling Technologies
交通大學電機系人才培訓班 本新聞稿發佈於2010/04/13,由發布之企業承擔內容之立場與責任,與本站無關

990424(週六開課)Key Enabling Technologies for 3D IC / Si Integrations 授課時間:授課時數及課程費用:優惠價4000元 授課日期:4/24-5/8每週(六) 09: 00~16: 30 報名請參閱http://web.cm.nctu.edu.tw/~cnc/course.php?ClassNo=99A12

 
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990424(週六開課)Key Enabling Technologies for 3D IC / Si Integrations
授課教師及職稱:劉漢誠 John H. Lau ( ITRI Fellow of ITRI since 2010... )
課程大綱:The key enabling technologies for 3D IC integration are, e.g., electrical, thermal, and mechanical designs and tests, known good die (KGD), TSV (through silicon via) forming and filling, wafer thinning and handling, thin chip strength measurement and improving, lead-free microbump forming and assembly, low temperature C2W and W2W bonding, and thermal management. In this course, all these enabling technologies (except electrical) will be discussed.

Moore's law has been the most powerful driver for the development of the microelectronic industry. This law emphasizes on lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC/Si integration, which is a very complicate subject. It involves component and system designs, FAB, packaging assembly and testing, material suppliers, and equipment suppliers. The key enabling technologies for 3D IC integration are, e.g., electrical, thermal, and mechanical designs and tests, known good die (KGD), TSV (through silicon via) forming and filling, wafer thinning and handling, thin chip strength measurement and improving, lead-free microbump forming and assembly, low temperature C2W and W2W bonding, and thermal management. In this course, all these enabling technologies (except electrical) will be discussed. Most of the materials are based on the technical papers published within the past 3 years by others and the instructor.

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聯絡人 :莊小姐
聯絡電話:(03)573-1747
電子郵件:cnc@cm.nctu.edu.tw

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